Semiconductor memory test pattern generating apparatus

ABSTRACT

A semiconductor memory test pattern generating apparatus in which an instruction memory is read out, assigning an address by a program counter, and instructions thus read out are decoded and executed to generate a test pattern. A start address and a stop address and index data indicating the number of times of executing an area defined by the start and stop addresses are stored in a loop memory. During the operation of the program counter the start and stop addresses and the index data are read out from the loop memory and loaded in a register group. When the program counter coincides with the loaded stop address, the setting of the program counter to the loaded start address is executed by the number of times indicated by the loaded index data, and in the last execution the next address of the loop memory is read out.

BACKGROUND OF THE INVENTION

The present invention relates to a test pattern generating apparatuswhich generates galloping, walking and various other test patterns fortesting semiconductor memories.

Conventional semiconductor memory test pattern generating apparatuseshave such a construction as proposed, for example, in U.S. patentapplication Ser. No. 26,246 now U.S. Pat. No. 4,293,950, (filed Apr. 2,1979) entitled "Test Pattern Generating Apparatus." In such a prior artexample, an instruction memory is read out by an address from an addresscounter and an address generating instruction in the output read outfrom the instruction memory is decoded and executed by an addressgenerator to generate an address pattern. A data generating instructionin the read output is decoded and executed by a data generator togenerate a data pattern. A memory under test is accessed by the addresspattern to read it out or to write therein the data pattern. Statusinformation from the address generator and the data generator, such asthe address pattern and the data pattern therefrom, and a conditionalbranch instruction in the output read out from the instruction memoryare provided to a control circuit. By a control signal from the controlcircuit, the address counter is controlled to step or set its content toa jump address in the output read out from the instruction memory.

With such a conventional test pattern generating apparatus, since thetime for obtaining the abovesaid control signal is included in theoperation period from the execution of an instruction to the executionof the next instruction, it is difficult to generate test patterns athigh speed. If the test is conducted at high speed, when the abovesaidjump takes place, there occurs what is called a dummy cycle in which notest pattern is applied to the memory under test. An appreciable numberof test patterns repeat the same sequence from a certain address toanother address of the memory under test, such as galloping, walking andlike patterns. In the case of repeating the same sequence, the addresscounter of the instruction memory is usually jump-controlled, so that inthe high-speed test, the dummy cycle often occurs, resulting in the testbecoming undesirably lengthy.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductormemory pattern generating apparatus which is capable of generating testpatterns at high speed.

Another object of the present invention is to provide a semiconductormemory test pattern generating apparatus which permits high-speedgeneration of test patterns of the type including repetition of the samesequence.

Yet another object of the present invention is to provide asemiconductor memory test pattern generating apparatus which permitshigh-speed generation of complex text patterns wherein repetition of thesame sequence is multiplexed.

According to the present invention, a start and a stop addressindicating an area to be accessed, index data indicating the number oftimes of accessing the area, and loop data indicating whether or not astart and a stop address of another loop to be accessed are includedbetween the start and the stop address, are written in a loop memory,and a plurality of sets of such data are written in the loop memory inthe order of execution. One of the sets is read out from the loop memoryto load the data in a start address register, a stop address registerand an index data register, respectively. An instruction memory in whichis loaded a microprogram having described therein a test pattern isaccessed in accordance with the content of a program counter. Whencoincidence is detected between the address of the program counter andthe content of the stop address register, the start address in theaddress register is set by a coincidence output into the program counterto start the incrementing of the program counter again, this is repeatedby the number of times indicated by the data set in the index dataregister. By providing a plurality of sets of such start addressregisters, stop address registers and index data registers and by usinga loop data register, it is also easy to arrange a double loop so that acertain area within, for example, the abovementioned access area isaccessed a predetermined number of times each time the abovesaid accessarea is accessed. In the case of providing such a plurality of sets ofregisters, by reading out the loop memory and loading the read outputinto another set of registers during the generation of a single-loop ordouble-loop pattern, various loop patterns can be generated with nodummy cycle.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a conventional pattern generatingapparatus;

FIG. 2 is a diagram showing the sequence of a galloping pattern;

FIG. 3 is a block diagram illustrating an embodiment of the test patterngenerating apparatus of the present invention;

FIG. 4 is a logic circuit diagram illustrating in detail an example of acontrol circuit 19 used in the embodiment of FIG. 3;

FIG. 5 is a diagram showing an example of the sequence of a testpattern; and

FIG. 6 is a diagram showing an example of the stored content of a loopmemory employed in the embodiment of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

To facilitate a better understanding of the present invention, adescription will be given of a conventional test pattern generatingapparatus.

A prior art test pattern generating apparatus for testing asemiconductor memory has a construction as shown in FIG. 1, which isdescribed in detail, for example, in the aforementioned U.S. patentapplication. The test pattern generating apparatus comprises aninstruction memory 1 which is loaded with a microprogram describing testpatterns to be generated, an address pattern generator 2 whichinterprets an instruction from the instruction memory 1 to generate anaddress pattern for accessing a memory under test 15, a data patterngenerator 3 which interprets an instruction from the instruction memory1 to generate a data pattern to be applied to the memory under test 15,a program counter 4 which generates an address for accessing theinstruction memory 1, and a control circuit 5 which controls the programcounter 4 in response to an instruction from the instruction memory 1,an address from the address pattern generator 2 and data from the datapattern generator 3.

The instruction memory 1 is accessed by a memory address 6 from theprogram counter 4 to provide an address generating instruction 7 to theaddress pattern generator 2, a data generating instruction 8 to the datapattern generator 3, a jump address 13 to the program counter 4 and aninstruction 12 to the control circuit 5. The address pattern generator 2interprets the address generating instruction 7 from the instructionmemory 1 to execute a predetermined arithmetic operation, outputting anaddress pattern 9 to the memory under test 15 and several kinds ofstatus information 10 indicating the status of the address patterngenerator 2. The data pattern generator 3 interprets the data generatinginstruction 8 from the instruction memory 1 to execute an arithmeticoperation, outputting a data pattern 11 to the memory 15 under test andseveral kinds of status information 10 indicating the status of the datapattern generator 3. The control circuit 5 generates, in accordance withthe instruction 12 from the instruction memory 1 and the statusinformation 10 from the address pattern generator 2 and the data patterngenerator 3, a control signal 14 for controlling the operation of theprogram counter 4.

The program counter 4 is controlled by the control signal 14 from thecontrol circuit 5 to provide, as the next memory address 6, the jumpaddress 13 from the instruction memory 1 or the address next to theaddress which is being outputted. During operation the memory address 6is applied from the program counter 4 to the instruction memory 1 toread out therefrom the content stored in the address indicated by thememory address 6, applying the address generating instruction 7, thedata generating instruction 8, the instruction 12 and the jump address13 in the read output to the address pattern generator 2, the datapattern generator 3, the control circuit 5 and the program counter 4,respectively. The address pattern generator 2 and the data patterngenerator 3 respectively interpret the address generating instruction 7and the data generating instruction 8 to execute predeterminedarithmetic operations, providing the address pattern 9 and the datapattern 11 to the memory 15 under text and the status information 10such as an address pattern, a data pattern, etc. to the control circuit5. The data pattern generator 3 interprets and executes the datagenerating instruction from the instruction memory 1 to provide the datapattern 11 to the memory 15 under test.

Based on the instruction 12 from the instruction memory 1 and the statusinformation 10, the control circuit 5 applies to the program counter 4the control signal 14 for controlling the address of the instructionmemory 1 to be accessed next. The program counter 4 outputs, as thememory address 6, an address next to the memory address 6 beingoutputted or the jump address 13 from the instruction memory 1 dependingon whether the control signal 14 is "0" or "1."

FIG. 2 shows the sequence of a galloping pattern used as a test patternfor a semiconductor memory. In FIG. 2, the ordinate represents addressesapplied to the memory 15 under test and the abscissa represents accesssequence. Reference character N indicates a maximum address of thememory 15 under test, W₀ and W₁ respectively show accesses for writingdata 0 and 1 in the addresses shown on the left-hand side, and R₀ and R₁respectively show accesses for reading out from the addresses the data 0and 1.

The galloping pattern can be obtained in such a manner as shown in FIG.2. At first "0" is written in all addresses 0 to N of the memory 15under test; "1" is written in the address 0, using it as a referenceaddress; all the addresses 0 to N are read out in the order of address1--reference address (address 0)--address 1; address 2--referenceaddress (address 0)--address 2; address 3--reference address (address0)--address 3; . . . ; and then "0" is written in the reference address,thus restoring all the addresses to "0." Thereafter, the above sequenceis repeated, using as the reference address the addresses 1 to N oneafter another.

With the conventional pattern generator, the galloping pattern isgenerated in the following manner. At first, the data "0" is written inall the addresses of the memory under test by executing a data "0"writing instruction N times while incrementing the address of the memoryand, after executing an instruction for writing data "1" in thereference address, a set of three instructions for reading out a triadof addresses in the order address M- reference address-address M areexecuted, using as the address M the addresses 0 to N one after anotherexcept the reference address, and then an instruction for writing "0" inthe reference address is executed. In this way, the above sequence isexecuted, using as the reference address the addresses 0 to N in asequential order.

In the prior art pattern generator, for executing the same instructionsN and M times in the above-described manner, use is made of a method ofcontrolling the program counter 4 by the status information 10, such asthe address data and the data pattern data from the address patterngenerator 2 and the data pattern generator 3 and the instruction 12 fromthe instruction memory 1, to execute the same instruction N times and aspecific instruction group M times.

Since the conventional semiconductor memory test pattern generatingapparatus adopts a method that interprets the program described in theinstruction memory to generate the address pattern and the data patternand, at the same time, produces the control signal 14 by the statusinformation from the address pattern generator and the data patterngenerator and a conditional branch instruction described in theinstruction memory, and then accesses an instruction to be executednext, as described above, the operation period from the execution of oneinstruction to the execution of the next instruction includes the timefor obtaining the control signal 14, making it difficult to achieve ahigh-speed operation.

FIG. 3 illustrates an embodiment of the test pattern generatingapparatus of the present invention. In FIG. 3, the instruction memory 1,the address pattern generator 2 and the data pattern generator 3 areidentical to those shown in FIG. 1. The program counter 4 generates thememory address 6 for accessing the instruction memory 1. The programcounter 4 has a function of incrementing its content in synchronism withan operating clock of a terminal 20 or loading a start address 45 from amultiplexer 16 depending on whether a control signal 44 from a controlcircuit 19 is "0" or "1." The output from the program counter 4 isapplied as the memory address 6 to the instruction memory 1 and firstand second coincidence circuits 18 and 17.

A loop memory 21 loads start and stop addresses indicating an area ofthe instruction memory 1 to be accessed, index data indicating thenumber of times of accessing the area and loop data indicating whetheror not start and stop addresses for other loops are included between theabovesaid start and stop addresses. The loop memory 21 is accessed by anaddress 46 from an address counter 22 to apply a start address 47, astop address 48, index data 49 and loop data 50 stored in the accessedaddress to a second start address register 23, a second stop addressregister 24, a second index counter 26 and a loop data register 25,respectively. The address counter 22 generates the address 46 foraccessing the loop memory 21 and increments its content by a second(denoting the correspondence to the "second" start and stop addressregisters, etc.) request signal 51 from an OR circuit 27. The secondstart address register 23 loads the start address 47 from the loopmemory 21 in response to the second rquest signal 51 from the OR circuit27, and applies its output 47 as a second start address 52 to a firststart address register 29 and the multiplexer 16. The first startaddress register 29 loads the second start address 52 in response to afirst request signal 53 from an OR circuit 28 and applies its output asa first start address 54 to the multiplexer 16.

The multiplexer 16 selects one of the first and second start addresses54 and 52 as the start address 45 for the program counter 4. Namely, themultiplexer 16 provides, as the start address 45, the first startaddress 54 or the second start address 52 depending on whether a controlsignal 55 from the control circuit 19 is "0" or "1", respectively. Thesecond stop address register 24 responds to the second request signal 51to load the stop address 48 from the loop memory 21 and provide, as itsoutput, a second stop address 56 to a first stop address register 31 andthe second coincidence circuit 17. The first stop address register 31responds to the first request signal 53 from the OR circuit 28 to loadthe second stop address 56 and apply it as a first stop address 57 tothe first coincidence circuit 18. The second coincidence circuit 17compares the memory address 6 and the second stop address 56 and, in thecase of coincidence, yields a second coincidence signal 58. The firstcoincidence circuit 18 compares the memory address 6 and the first stopaddress 57 and, in the case of coincidence, produces a first coincidencesignal 59.

The loop data register 25 loads loop data indicating that the firststart address 54 and the first stop address 57 are included in the areadefined by the second start address 52 and the second stop address 56.The loop data register 25 responds to the second request signal 51 fromthe OR circuit 27 to load the loop data 50 from the loop memory 21 andprovides, as its output, loop data 60 to the control circuit 19. Thesecond index counter 26 indicates the number of times of accessing thearea defined by the second start address 52 and the second stop address56 and responds to the second request signal 51 from the OR circuit 27to load the index data 49. Further, the second index counter 26 respondsto a second DEC signal 61 from the control circuit 19 to decrement itscontent in synchronism with the operating clock at the terminal 20 andapplies a second ZERO signal 62 to the control circuit 19 whendecremented "0."

A buffer register 32 loads the content of the second index counter 26upon occurrence of the first request signal 53 from the OR circuit 28. Afirst index counter 33 indicates the number of times of accessing thearea defined by the first start address 54 and the first stop address 57and responds to a load signal 63 from an OR circuit 34 to load bufferdata 64 from the buffer register 32. Further, the index counter 33 alsoresponds to a first DEC signal 65 from the control circuit 19 todecrement its content in synchronism with the operating clock at theterminal 20 and provides a first ZERO signal 66 to the control circuit19 when decremented to "0." The output from the OR circuit 28 isprovided via a delay circuit 35 to the OR circuit 34. Terminal 36 isapplied with an initial clock for loading, at the start of operation, inthe respective registers the start address, the stop address, the indexdata and the loop data described in the loop memory 21.

FIG. 4 illustrates in detail the circuit arrangement of the controlcircuit 19. When the first coincidence signal 59 is obtained and aflip-flop 72 is reset, an AND circuit 71 produces the first DEC signal65 for decrementing the first index counter 33 and, at the same time,yields via an OR circuit 73 the control signal 44 for loading the startaddress 45 in the program counter 4. When the second coincidence signal58 is provided and a flip-flop 75 is reset, an AND circuit 74 producesthe second DEC signal 61 for decrementing the second index counter 26and, at the same time, yields via the OR circuit 73 the control signal44 for loading the start address 45 in the program counter 4. Theflip-flops 72 and 75 are both synchronous set/reset flip-flops. Theflip-flop 72 is set via an AND circuit 76 in synchronism with theoperating clock at the terminal 20 when the first coincidence signal 59is provided and the first ZERO signal 66 is "1;" and when the secondcoincidence signal 58 is provided and the flip-flop 75 is not set, orwhen the loop data 60 is "0" and the flip-flop 72 is set, the flip-flop72 is reset via an OR circuit 77 in synchronism with the operating clockat the terminal 20. The flip-flop 75 is set via an AND circuit 78 insynchronism with the operating clock at the terminal 20 when the secondcoincidence signal 58 is provided and the second ZERO signal 62 is "1,"and the flip-flop 75 thus set is reset by the next operating clock.

The Q output from the flip-flop 72 is applied to AND circuits 79 and 81.When the loop data 60 from the loop data register 25 is "0," the firstrequest signal 68 is applied via AND circuits 79 and 82 to the ORcircuit 28 (FIG. 3), and the second request signal 67 is applied to theOR circuit 27 (FIG. 3) via the AND circuit 79, an OR circuit 85 and anAND circuit 86. When the loop data 60 is "1," the AND circuit 79 isinhibited by an inverter 87 and neither of the request signals 68 and 67is outputted, but the select signal 55 is provided to the multiplexer 16for outputting therefrom, as the start address 45, the start address 52from the second start address register 23. The Q output from theflip-flop 75 is applied as the second request signal 67 to the ORcircuit 27 (FIG. 3) via the OR circuit 85 and the AND circuit 86.

FIG. 5 shows an example of an address sequence of the instruction memory1 which is generated by the test pattern generating apparatus of FIG. 3.As shown in FIG. 5, after an access is made from an address 0 to anaddress a and thence to an address b, an access is made from the addressb to an address c n1 times and thence to an address d, thereafterreturning to the address a. This sequence is executed n2 times in all.FIG. 6 shows start addresses, stop addresses, index data and loop datawhich are described in the loop memory 21 for generating the sequenceshown in FIG. 5.

Next, a description will be given of the operation of FIG. 3 inconnection with the case of generating the address sequence for theinstruction memory, shown in FIG. 5. Prior to the starting of operation,the data shown in FIG. 6 are transferred to the loop memory 21 and "0"is set in the program counter 4. At the start of operation, the initialclock is applied to the terminal 36 twice to read out data stored inaddresses 0 and 1 of the loop memory 21. Thus setting by the first andsecond request signals 53 and 51, b in the first start address register29, a in the second start address register 23, c in the first stopaddress register 31, d in the second stop address register 24, "1" inthe loop data register 25, n2-2 in the second index counter 26, n1-2 inthe buffer register 32 and n1-2 in the first index counter 33.

Next, when the operating clock is applied to the terminal 20, theprogram counter 4 increments in synchronism with the operating clockwhile the control signal 44 is "0." Then, when the memory address 6 fromthe program counter 4 coincides with the stop address c loaded in thefirst stop address register 31, the first coincidence signal 59 from thefirst coincidence circuit 18 become "1" and is provided to the ANDcircuit 71 (FIG. 4). At this time, since the flip-flop 72 (FIG. 4) isnot set, and AND circuit 71 applies the coincidence signal as thecontrol signal 44 to the program counter 4 (FIG. 3) and as the first DECsignal 65 to the first index counter 33.

By the control signal 44 being "1", the start address b stored in thefirst start address register 29 is loaded in the program counter 4 viathe multiplexer 16. When the address b is set in the program counter 4,the memory address 6 becomes b and the first coincidence signal 59 fromthe first coincidence circuit 18 becomes "0," so that the control signal44 also becomes "0," returning the program counter 4 to the incrementingmode. On the other hand, when the first coincidence signal 59 from thefirst coincidence circuit 18 is "1," the first DEC signal 65 is appliedfrom the AND circuit 71 (FIG. 4) to the first index counter 33 (FIG. 3)to cause it to decrement in synchronism with the operating clock.

Next, when the content of the first index counter 33 becomes "0" and thefirst ZERO signal 66 is provided to the control circuit 19 and thememory address 6 matches with the stop address c to yield the firstcoincidence signal 59, the control signal 44 is supplied via the ANDcircuit 71 (FIG. 4) and the OR circuit 73 (FIG. 4) to the programcounter 4 (FIG. 3) to load therein the start address b. Thereafter, theflip-flop 72 (FIG. 4) is set by the output from the AND circuit insynchronism with the operating clock (20), and the data from the ANDcircuit 76 is applied as a buffer load signal 69 to the OR circuit 34(FIG. 3) and the data n1-2 stored in the buffer register 32 is loaded inthe first index counter 33.

The Q terminal of the flip-flop 72 (FIG. 4) is connected to the ANDcircuits 79 and 81, and the Q terminal is connected to the AND circuit71, which inhibits the first coincidence signal 59 after the flip-flop72 is set. Accordingly, the memory address from the program counter 4proceeds to an address c+1 next to the address c. Upon setting of theflip-flop 72, since the loop data 60 from the loop data register 25(FIG. 3) is "1," the AND circuit 81 (FIG. 4) applies to the multiplexer16 (FIG. 3) the control signal 55 for selecting a in the second startaddress register 23.

As explained above, when an address produced by the program counter 4coincides with the first stop address c, the first start address b isloaded in program counter 4 (i.e., a jump operation is implemented) atthe same time the content of the first index counter 33 is decremented.However, despite the fact that the address produced by the programcounter 4 coincides with the first stop address c with the first indexcounter 33 being "0," the flip-flop 72 is not set until the operatingclock is supplied thereto. Therefore, the coincidence signal 59instantly causes to produce a control signal 44 via the AND circuit 71and the OR circuit 73, and thereafter the flip-flop 72 is set insynchronism with the first operating clock from the terminal 20 afterthe set signal from the gate circuit 76 is supplied to the flip-flop 72.This means that even though the content of the first index counter 33becomes "0," another loading of the first start address to the programcounter 4 takes place. Accordingly, the jump operations are carried outa number of times one more than the set value (n₁ -2) in the first indexcounter 33, that is, if the jump operation between the addresses b and cis performed (n₁ -1) times, then this allows access between theaddresses b and c n₁ times. Consequently, according to the practicalembodiment shown in FIGS. 3 and 4, in order to access the addressesbetween b and c n₁ , or to jump from c to b a number of times (n₁ -1)times, (n₁ -2) is preset in the first index counter 33.

Next, when the memory address 6 coincides with the stop address d, thesecond coincidence signal 58 is provided. Upon occurrence of the secondcoincidence signal 58, the control signal 44 is applied via the ANDcircuit 74 (FIG. 4) and the OR circuit 73 to the program counter 4 toload therein the start address a selected by the multiplexer 16 inaccordance with the logic "1" of the select signal 55 derived from theAND circuit 81. On the other hand, the signal from the AND circuit 74 isprovided via the OR circuit 77 to the R terminal of the flip-flop 72,which is reset by the operating clock provided immediately after theoccurrence of the second coincidence signal 58. When the flip-flop 72 isreset, the control signal 55 from the AND circuit 81 becomes "0" and theaddress b in the first start address register 29 (FIG. 3) is selectedagain by the multiplexer 16, as the start address 45. Further, theoutput from the AND circuit 74 (FIG. 4) is applied as the second DECsignal 61 to the second index counter 26 (FIG. 3) to cause it todecrement by one in synchronism with the operating clock. Since theaddress in the memory address 6 becomes the address a as mentioned aboveupon setting the address a, the second DEC signal 61 and the controlsignal 44 both become "0." When the control signal 44 becomes "0," theprogram counter 4 increments from the address a.

After repeating the above operation, when the content of the secondindex counter 26 becomes "0" to provide the second ZERO signal 62 andthe memory address 6 coincides with the stop address d to yield thesecond coincidence signal 58, the control signal 44 is applied via theAND circuit 74 (FIG. 4) and the OR circuit 73 to the program counter 4(FIG. 3) to load therein the start address a. The flip-flop 75 (FIG. 4)is set via the AND circuit 78 at the timing of the operating clock andreset by the next operating clock. The Q output from the flip-flop 75 isprovided as the second request signal 67 via the OR circuit 85 and theAND circuit 86. When the second request signal 67 is thus yielded, newdata described in the address 2 of the loop memory 21 (FIG. 3) areloaded, by the second request signal 51 from the OR circuit 27, into thesecond address register 23, the second stop address register 24, theloop data register 25 and the second index counter 26, and the addresscounter 22 increments to indicate the next address.

Next, when the content of the first index counter 33 is "0" to yield theZERO signal 66 and the address produced by the program counter 4coincides with the first stop address c to yield the first coincidencesignal 59, the flip-flop 72 (FIG. 4) is set to produce the Q output.However, since the loop data signal 60 is "0" as a result of thecontents of address 2 in the loop memory 21, (FIG. 3) being loaded intothe respective registers 23, 24 and 25 as mentioned before, the Q outputof the flip-flop 72 is inhibited by the AND circuit 81 thus yielding "0"for the selection signal 55. On the other hand, since the AND circuit 79(FIG. 4) is supplied with the inversion of the loop data 60 (set to 1 bythe above described load of data from memory location 2) therefore, theoutput from the flip-flop 72 is provided via the AND circuit 79 to theOR circuits 77 and 85 and the AND circuit 82. The output from the ORcircuit 77 is provided to the R terminal of the flip-flop 72 and theflip-flop 72 is reset by the next operating clock. The output from theOR circuit 85 is applied to the AND circuit 86, deriving the requestsignals 68 and 67 from the AND circuits 82 and 86.

When the request signals 68 and 67 are thus produced, the first andsecond request signals 53 and 51 are respectively provided from the ORcircuits 28 and 27, (FIG. 3) by which the contents of the second startaddress register 23, the second stop address register 24 and the secondindex counter 26 are respectively loaded into the first start addressregister 29, the first stop address register 31, and the first indexcounter 33 and the buffer register 32; namely, the data which have beenread from the address 2 of the loop memory 21 into the respective secondregisters 23, 24 and second counter 26 are loaded with respective firstregisters 29, 31 and the first counter 33. Thus data stored in theaddress 3 of the loop memory 21 are newly loaded in the second startaddress register 23, the second stop address register 24, the secondindex counter 26 and the loop data register 25. By the operating clockfollowing the occurrence of the first coincidence signal 59, the startaddress b before the above-mentioned rewriting of the first addressregister 29, is loaded in the program counter 4, which increments fromthe next working clock.

As described above, the pattern generating apparatus of this embodimenthas registers for loading pairs of start addresses, stop addresses andindex data and two sets of circuits for executing the operation ofsetting the pair of start addresses in the program counter 4 uponcoincidence of the memory address from the program counter 4 with thestop address by the number of times indicated by the index data. By theloop data a multiple loop is enabled and, at the same time, theregisters in which start and stop addresses and loop data having becomeunnecessary are reloaded by data from the loop memory, by which addresssequences, each having plural loops are generated. In addition, sincethe reloading of the registers takes place during the execution of thelast one of the loop operations to be executed, it is possible toexecute a new loop operation immediately after the execution of thatlast loop operation.

With the pattern generating apparatus of the present invention, in thecase of generating an address sequence having a plurality of loops, thestart address from the start address register is loaded in the programcounter when the memory address from the program counter coincides withthe stop address from the stop address register and, after executingthis operation a plurality of times, the start address and the stopaddress are replaced with new ones, so that no memory access is neededduring the operation period, permitting a high-speed operation. In theprior art a branch instruction is obtained for the first time afterdecoding and executing an address generating instruction and a datagenerating instruction, and the program counter is jumped. In thepresent invention, however, a certain one of loops and the next addressof the loop memory is read out during the execution of the last one ofthe loops to be executed, so that the jump of the program counter isperformed immediately without awaiting the decoding and execution of theaddress generating instruction and the data generating instruction;accordingly, semiconductor memories can be tested by high-speedoperations.

It will be apparent that many modifications and variations may beeffected without departing from the scope of the novel concepts of thisinvention.

What is claimed is:
 1. A test pattern generating apparatus forselectively repeating selected sequences of instructions in amicroprogram for testing a memory under test, said apparatuscomprisingan instruction memory for storing said instructions of saidmicroprogram at respective addresses, said instructions of saidmicroprogram comprising address and data generating instructions, aprogram counter coupled to said instruction memory for providing thesequence of addresses of the instruction memory to be accessed forproviding said repeated sequences of said instructions for selectivelytesting said memory under test, an address pattern generator coupled tosaid instruction memory for decoding and executing each said accessedaddress generating instruction and for generating a correspondingaddress pattern to be applied to said memory under test, a data patterngenerator coupled to said instruction memory for decoding and executingeach said accessed data generating instruction and for generating acorresponding data pattern to be applied to the memory under test, aloop memory for storing at respective addresses a plurality of sets ofloop pattern data for defining said repeated sequences of saidinstructions, said sets of loop pattern data including first setsthereof, each said first set comprising a first start address and afirst stop address indicating a corresponding area of the instructionmemory to be sequentially accessed between said first start and stopaddresses, and first index data indicating the number of times therespective area is to be accessed, an address counter coupled to saidloop memory for sequentially generating the addresses of the loop memoryto be accessed for generating said repeated sequences of saidinstructions, a first set of registers, each coupled to said loopmemory, including a first start address register, a first stop addressregister and a first index data register for sequentially storing thefirst start address, the first stop address and the first index data ofeach respective first set of loop pattern data that is accessed by saidaddress counter, said first start address register being coupled betweensaid loop memory and said program counter, and said first stop addressregister and said first index data register being coupled to said loopmemory, a first coincidence circuit coupled to said first stop addressregister and to said program counter for comparing the first stopaddress loaded in the first stop address register with the currentaddress in the program counter, for detecting coincidences therebetweenand for outputting a corresponding first coincidence signal upon eachsaid coincidence, and a control circuit, coupled to said addresscounter, to each of said first set of registers and to said programcounter, and comprising means for setting each said first start addressstored in the first start address register into the program counterresponsive to said first coincidence signal for a predetermined numberof said first coincidence signals indicated by the respective firstindex data that was set in the first index data register, forincrementing the content of the address counter, and for replacing thecontents of the first start address register, the first stop addressregister and the first index data register with the respective values ofthe subsequent first set of said loop pattern data that is accessed bysaid address counter, wherein said selected repeated sequences of saidinstructions of said test pattern are generated by said apparatus forselectively testing said memory under test according to the accessing ofsaid instruction memory the respective number of times indicated by eachsaid first index data between the respective first start and stopaddresses of said loop pattern data in the order of said accessing ofsaid loop memory by said address counter.
 2. The apparatus of claim 1,comprisingsaid loop memory also storing second sets of said loop patterndata, each said second set of loop pattern data comprising a secondstart address, a second stop address and a second index data, each ofsaid first and second sets of loop pattern data effectively comprisingalso respectively different loop data values, each said loop data valueof a second set being for effectively indicating that a respectiverepeated sequence of said instructions corresponding to a respectivefirst set of said loop pattern data is to be performed within eachrepeated sequence of the respective second set, the area of saidinstruction memory defined by the first start and stop addresses of eachsaid respective first set lying within the area thereof defined by thesecond start and stop addresses of the respective second set, a secondset of registers including a second start address register, a secondstop address register, a second index data register and a loop dataregister for respectively storing the start address, the stop address,the index data and the loop data of at least each of said second loopdata sets that is accessed by said address counter from the loop memory,said second start address register being coupled between said loopmemory and said first start address register, said second stop addressregister being coupled between said loop memory and said first stopaddress register, said second index counter being coupled between saidloop memory and said first index data counter, each register of saidsecond set of registers also being coupled to said control circuit, asecond coincidence circuit, coupled to said second stop address registerand to said program counter, for comparing each said second stop addressin the second stop address register with the address from the programcounter, for detecting each coincidence therebetween, and for outputtinga corresponding second coincidence signal upon each respectivecoincidence, and said control circuit further comprising means forsetting each said second start address loaded in the second startaddress register into the program counter when said second coincidencesignal is output from the second coincidence circuit for a respectivepredetermined number of times as indicated by the respective secondindex data in the second index data register, and for performing theaccessing of said area of said instruction memory corresponding to thefirst start and stop addresses and the first index data of therespective first set of said loop pattern data stored in said first setof registers during each sequence of accessing said instruction memoryin the area corresponding to said second start and stop addresses of therespective second set of said loop pattern data, wherein said repeatedsequences of said instructions of said microprogram are selectivelygenerated for said selective testing of said memory under test,corresponding to the sequentially accessed first and second loop patterndata sets in the loop memory.
 3. The apparatus of claim 2, said controlcircuit further comprising means for storing each said first set of looppattern data that is accessed by said address counter in the respectiveones of said second set of registers and for subsequently transferringeach said first start and stop addresses and the first index data of thefirst set of loop pattern data to said first set of registers forperforming the respective repeated sequence of instructionscorresponding thereto, said apparatus comprisinga buffer registercoupled between said first and second index data registers for receivingeach said first index data from the second index data register and fortransferring same into the first index data register, and said controlcircuit further comprisingfirst decrementing means for decrementing thecontent of the first index data register in response to the firstcoincidence signal down to a first predetermined value, seconddecrementing means for decrementing the content of the second index dataregister in response to the second coincidence signal down to a secondpredetermined value, first index data transfer means for controllingtransfer of the content of the buffer register into the first index dataregister in response to the occurrence of coincidence between said firstpredetermined value of the content of the first index data register andthe coincidence signal output from the first coincidence circuit,inhibit means for inhibiting the supply to the control circuit, for saidcontrolling by the first index data transfer means, of the firstoccurrence of the coincidence signal output from the first coincidencecircuit after each said coincidence between the occurrence of thepredetermined value of the decremented content of the first index dataregister and said output from the first coincidence circuit, and meansfor releasing the inhibiting of the inhibit means in response to thefirst occurrence of said coincidence signal output from the secondcoincidence circuit after each said inhibiting, wherein the loading intothe program counter of the start address from the first or second startaddress register is controlled to perform said repeated accessing ofeach said area of said instruction memory, corresponding to each one ofsaid second sets of loop pattern data that is stored in said second setof registers and to each first set of loop pattern data that is storedin said first set of registers.
 4. The apparatus of claim 3, saidcontrol system further comprisingmeans for determining, dependent on thecontent of the loop data register, whether the next set of loop patterndata from the loop memory is to be read out, in response to each saidcoincidence between the occurrence of said predetermined value of thecontent of the first index data register and the coincidence signal fromthe first coincidence circuit, and means, when one of said first sets ofloop pattern data is currently being stored in said second registers,for reading into said second set of registers the respective subsequentone of said loop pattern data sets accessed by said address counter, andfor storing in said first set of registers the first start and stopaddresses and the first index data of the first set of loop pattern datathat is currently stored in said second registers.
 5. The apparatus ofclaim 3, said means for releasing said inhibiting including means forreleasing said inhibiting in accordance with the content of said loopdata register.
 6. The apparatus of claim 2, 3 or 4, said control circuitfurther comprising means for reading out the next address of the loopmemory during the completion of the last sequence of each of therepeated sequences of instructions then being performed, wherein nodummy cycles are required for providing said instruction for testingsaid memory.
 7. The apparatus of claim 2, 3 or 4, said control circuitfurther comprising means for controlling said address counter, when saidrepeated sequences of instructions that are being generated correspondto a respective pair of said first and second sets of loop pattern data,(1) to access the next set of said loop pattern data in said loopmemory, for loading said next set of loop pattern data into said secondset of registers during the last sequence of said repeated instructionscorresponding to said second set of loop pattern data of said pair, and(2) to access the further next set of said loop pattern data in saidloop memory during the last sequence of said repeated instructionscorresponding to said first set of loop pattern data of said pair, andfor loading said further next set into said second set of registerswhile loading the respective members of said next set into said firststart and stop address and first index data registers.